The prior arts of flash memory devices, such as the ETOX™ flash memories of Intel and/or contact-less flash memories of other companies, have utilized the structure of Floating Gate/ONO dielectric/Control Gate stack in the memory cell. Please refer to FIG. 1, wherein the manufacturing processes of forming a semi-conductor structure like a flash memory using conventional hard-masking etching scheme will include steps of: (a) providing a substrate 200; (b) forming on the substrate an oxide layer 201, a first conductive layer 202, a first dielectric layer 203, a second conductive layer 204, and a second dielectric layer 205 sequentially; (c) etching the second dielectric layer 205, the second conductive layer 204, the first dielectric layer 203, and the first conductive layer 202 for forming a first recess pattern 206, and so on. The sizes of the memory cells are measured by the widths of the first recess patterns 206 or the widths of the word-lines 207. These prior arts have encountered issues while attempting to scale down the sizes of such memory cells to the 0.18/0.13/0.1 um generations. For example, high aspect ratio has been encountered in etching the FG/ONO/CG stack, requiring the introduction of hard-mask etching scheme. It has encountered therefore even higher aspect ratio in the gap-filling of memory cells after FG/ONO/CG etching steps. Scaling of flash memory cells requires new structure and integration scheme of forming the FG/ONO/CG stack and associated word-lines, which connect the control gates in a flash memory cell array. Another issue accompanied with the scaling of flash memory cell is that the word-line resistance will increase substantially as the device scaled down to 0.13/0.1 um generations if using the conventional doped poly-Si (with Ti Salide or Co Salide) or W-polycide as the materials of control gates and word-lines. A low resistance material like W or AlCu shall be introduced as the word-lines and therefore it requires a new structure and integration scheme of forming the control gates and word-lines in a flash memory cell arrays. The Patents related to the prior arts include: U.S. Pat. Nos. 6,172,912, 6,215,699, 6,185,131, and 5,962,890.
Employing W/TiN/Doped-Poly-Si stack as the control gates and word-lines in non-volatile memory cell arrays, a scalable structure and an integration scheme with word-lines of low resistance could be formed. Utilizing the doped-poly-Si/ONO/thin doped-poly-Si stack while performing the etching and gap-filling of the FG/ONO/CG cell stacks could create easier processes with lower aspect ratios compared to conventional W-polycide with hard-mask processes. Also, the aspect ratio of field isolation implant (using contact-less cells) is decreased in the proposed scheme.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the structure and the manufacturing method of non-volatile semiconductor memory device are finally conceived by the applicant.